ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 129
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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13. I/O Ports
13.1
13.2
8077H–AVR–12/09
Features
Overview
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XMEGA has flexible General Purpose I/O (GPIO) Ports. A port consists of up to 8 pins ranging
from pin 0 to 7, where each pin can be configured as input or output with highly configurable
driver and pull settings. The ports also implement several functions including interrupts, synchro-
nous/asynchronous input sensing and asynchronous wake-up signalling.
All functions are individual per pin, but several pins may be configured in a single operation. All
ports have true Read-Modify-Write (RMW) functionality when used as general purpose I/O ports.
The direction of one port pin can be changed without unintentionally changing the direction of
any other pin. The same applies when changing drive value when configured as output, or
enabling/disabling of pull-up or pull-down resistors when configured as input.
Figure 13-1 on page 130
controlling a pin.
Selectable input and output configuration for each pin individually
Flexible pin configuration through dedicated Pin Configuration Register
Synchronous and/or asynchronous input sensing with port interrupts and events
Asynchronous wake-up signalling
Highly configurable output driver and pull settings:
Slew rate control
Flexible pin masking
Configuration of multiple pins in a single operation
Read-Modify-Write (RMW) support
Toggle/clear/set registers for OUT and DIR registers
Clock output on port pin
Event Channel 0 output on port pin 7
Mapping of port registers (virtual ports) into bit accessible I/O memory space
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–
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Totem-pole
Pull-up/-down
Wired-AND
Wired-OR
Bus keeper
Inverted I/O
shows the I/O pin functionality, and the registers that is available for
XMEGA A
129
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