ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 49
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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5. DMA - Direct Memory Access Controller
5.1
5.2
8077H–AVR–12/09
Features
Overview
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The XMEGA Direct Memory Access (DMA) Controller is a highly flexible DMA Controller capable
of transferring data between memories and peripherals with minimal CPU intervention. The
DMA controller has flexible channel priority selection, several addressing modes, double buffer-
ing capabilities and large block sizes.
The DMA Controller can move data between memories and peripherals, between memories and
between peripheral registers directly.
There are four DMA channels that have individual source, destination, triggers and block sizes.
The different channels also have individual control settings and individual interrupt settings and
interrupt vectors. Interrupt requests may be generated both when a transaction is complete or if
the DMA Controller detects an error on a DMA channel. When a DMA channel requests a data
transfer, the bus arbiter will wait until the AVR CPU is not using the data bus and permit the DMA
Controller to transfer data. Transfers are done in bursts of 1, 2, 4 or 8 bytes. Addressing can be
static, incremental or decremental. Automatic reload of source and/or destination address can
be done after each burst transfer, block transfer, when transmission is complete, or disabled.
Both application software, peripherals and Events can trigger DMA transfers.
The DMA Controller allows high-speed transfers with minimal CPU intervention
Four DMA Channels with separate
From 1 byte to 16M bytes data transfer in a single transaction
Up to 64 KByte block transfers with repeat
1, 2, 4, or 8 byte burst transfers
Internal and external transfer triggers
Multiple addressing modes
Optional reload of source and destination address at the end of each
Optional Interrupt on end of transaction
Programmable channel priority
– from one memory area to another
– from memory area to peripheral
– from peripheral to memory area
– from peripheral to another peripheral
– transfer triggers
– interrupt vectors
– addressing modes
– Static
– Increment
– Decrement
– Burst
– Block
– Transaction
XMEGA A
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