ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 228
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.11 Register Summary - TWI
19.12 Register Summary - TWI Master
19.13 Register Summary - TWI Slave
19.14 Interrupt Vector Summary
Table 19-9.
8077H–AVR–12/09
Address
Address
Address
+0x00
+0x01
+0x08
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
Offset
0x00
0x02
Name
Name
Name
ADDRMASK
MASTER
STATUS
STATUS
CTRLC
SLAVE
CTRLA
CTRLB
CTRLA
CTRLB
TWI Interrupt vectors and their word offset addresses
BAUD
ADDR
ADDR
CTRL
DATA
DATA
Source
SLAVE_vect
MASTER_vect
Bit 7
Bit 7
Bit 7
RIF
DIF
-
-
-
-
INTLVL[1:0]
INTLVL[1:0]
Bit 6
Bit 6
Bit 6
APIF
WIF
-
-
-
-
Interrupt Description
TWI Slave Interrupt vector
TWI Master Interrupt vector
CLKHOLD
CLKHOLD
Bit 5
Bit 5
Bit 5
RIEN
DIEN
-
-
-
-
ADDRMASK[7:1]
Offset address for TWI Master
Offset address for TWI Slave
RXACK
RXACK
Bit 4
Bit 4
Bit 4
APIEN
WIEN
-
-
-
-
ADDR[7:0]
ADDR[7:0]
BAUD[7:0]
DATA[7:0]
DATA[7:0]
ARBLOST
ENABLE
ENABLE
Bit 3
Bit 3
Bit 3
COLL
-
-
-
TIMEOUT[1:0]
BUSERR
BUSERR
ACKACT
ACKACT
Bit 2
Bit 2
Bit 2
PIEN
-
-
SDAHOLD
TPMEN
Bit 1
Bit 1
Bit 1
QCEN
DIR
-
BUSSTATE[1:0]
CMD[1:0]
CMD[1:0]
ADDREN
XMEGA A
Bit 0
EDIEN
Bit 0
SMEN
Bit 0
SMEN
AP
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