ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 282
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8077H–AVR–12/09
• Bit 7:6 - MRDLY[1:0]: SDRAM Mode Register Delay
These bits select the delay between Mode Register command and an Activate command in
number of Peripheral 2x clock (CLK
Table 24-11. SDRAM Column Bits settings
• Bit 5:3 - ROWCYCDLY[2:0]: SDRAM Row Cycle Delay
These bits select the delay between a Refresh and an Activate command in number of Periph-
eral 2x clock (CLK
Table 24-12. SDRAM Row Cycle Delay settings
• Bit 2:0 - RPDLY[2:0]: SDRAM Row to Pre-charge Delay
RPDLY defines the delay between a Pre-charge command and another command in number of
Peripheral 2x clock (CLK
Table 24-13. SDRAM Row Cycle Delay settings
ROWCYDLY[2:0]
MRDLY[1:0]
RPDLY[2:0]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
00
01
10
11
PER2
) cycles, according to
Group Configuration
0CLK
1CLK
2CLK
3CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
PER2
) cycles, according to
PER2
) cycles, according to
Table 24-12 on page
Description
0 CLK
1 CLK
2 CLK
3 CLK
Description
0 CLK
1 CLK
2 CLK
3 CLK
4 CLK
5 CLK
6 CLK
7 CLK
Description
0 CLK
1 CLK
2 CLK
3 CLK
4 CLK
5 CLK
6 CLK
7 CLK
Table 24-13 on page
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
Table 24-11 on page
282..
282.
XMEGA A
282.
282
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