ATxmega16A4 Atmel Corporation, ATxmega16A4 Datasheet - Page 225
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ATxmega16A4
Manufacturer Part Number
ATxmega16A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16A4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16A4U-AU
Manufacturer:
SAMSUNG
Quantity:
514
Part Number:
ATxmega16A4U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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XMEGA A
• Bit 7 - DIF: Data Interrupt Flag
The Data Interrupt Flag (DIF) is set when a data byte is successfully received, i.e. no bus error
or collision occurred during the operation. Writing a one to this bit location will clear the DIF.
When this flag is set the slave forces the SCL line low, stretching the TWI clock period. Clearing
the interrupt flags will release the SCL line.
This flag is also automatically cleared when writing a valid command to the CMD bits in the
CTRLB register
• Bit 6 - APIF: Address/Stop Interrupt Flag
The Address/Stop Interrupt Flag (APIF) is set when the slave detects that a valid address has
been received, or when a transmit collision is detected. If the PIEN bit in the CTRLA register is
set a STOP condition on the bus will also set APIF. Writing a one to this bit location will clear the
APIF. When this flag is set the slave forces the SCL line low, stretching the TWI clock period.
Clearing the interrupt flags will release the SCL line.
The flag is also automatically cleared for the same condition as DIF.
• Bit 5 - CLKHOLD: Clock Hold
The slave Clock Hold (CLKHOLD) flag is set when the slave is holding the SCL line low.This is a
status flag, and a read only bit that is set when the DIF or APIF is set. Clearing the interrupt flags
and releasing the SCL line, will indirectly clear this flag.
• Bit 4 - RXACK: Received Acknowledge
The Received Acknowledge (RXACK) flag contains the most recently received acknowledge bit
from the master. This is a read only flag. When read as zero the most recent acknowledge bit
from the maser was ACK, and when read as one the most recent acknowledge bit was NACK.
• Bit 3 - COLL: Collision
The slave Collision (COLL) flag is set when slave is not been able to transfer a high data bit or a
NACK bit. If a collision is detected, the slave will commence its normal operation, disable data
and acknowledge output, and no low values will be shifted out onto the SDA line. Writing a one
to this bit location will clear the COLL flag.
The flag is also automatically cleared when a START or Repeated START condition is detected.
• Bit 2 - BUSERR: TWI Slave Bus Error
The slave Buss Error (BUSERR) flag is set when an illegal bus condition has occurs during a
transfer. An illegal bus condition occurs if a Repeated START or STOP condition is detected,
and the number of bits from the previous START condition is not a multiple of nine. Writing a one
to this bit location will clear the BUSERR flag.
For bus errors to be detected, the bus state logic must be enabled. This is done by enable TWI
master.
• Bit 1 - DIR: Read/Write Direction
The Read/Write Direction (DIR) flag reflects the direction bit from the last address packet
received from a master. When this bit is read as one, a Master Read operation is in progress.
When read as zero a Master Write operation is in progress.
225
8077H–AVR–12/09
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