ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 135
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega192D3-AU
Manufacturer:
CYPRESS
Quantity:
101
Company:
Part Number:
ATxmega192D3-AU
Manufacturer:
ATMEL
Quantity:
70
Company:
Part Number:
ATxmega192D3-H
Manufacturer:
SQ
Quantity:
719
Company:
Part Number:
ATxmega192D3-MH
Manufacturer:
Atmel
Quantity:
565
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12.9
8210B–AVR–04/10
Interrupts and events
Figure 12-15. Port override for Timer/Counter 0 and 1
The T/C can generate both interrupts and events. The Counter can generate an interrupt on
overflow/underflow, and each CC channel has a separate interrupt that is used for compare or
capture. In addition the T/C can generate an error interrupt if any of the CC channels is used for
capture and a buffer overflow condition occurs on a capture channel.
Event will be generated for all conditions that can generate interrupts. For details on event gen-
eration and available events refer to
WG 0A
WG 0B
WG 0C
WG 0D
WG 1A
WG 1B
CCENA
CCENB
CCENC
CCEND
CCENA
CCENB
”Event System” on page
OUTx0
OUTx1
OUTx2
OUTx3
OUTx4
OUTx5
INVENx0
INVENx1
INVENx2
INVENx3
INVENx4
INVENx5
44.
OC0A
OC0B
OC0C
OC0D
OC1A
OC1B
Px0
Px1
Px2
Px3
Px4
Px5
XMEGA D
135
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