ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 267
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Part Number
Manufacturer
Quantity
Price
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Manufacturer:
CYPRESS
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101
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Part Number:
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70
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Part Number:
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Manufacturer:
SQ
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719
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Part Number:
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Manufacturer:
Atmel
Quantity:
565
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22.5
22.5.1
22.5.2
8210B–AVR–04/10
Register Description - PDI Instruction and Addressing Registers
Instruction Register
Pointer Register
Figure 22-10. PDI instruction set summary
These registers are all internal registers that are involved in instruction decoding or PDIBUS
addressing. None of these registers are accessible as register in a register space.
When an instruction is successfully shifted into the physical layer shift-register, it is copied into
the Instruction Register. The instruction is retained until another instruction is loaded. The rea-
son for this is that the REPEAT command may force the same instruction to be run repeatedly
requiring command decoding to be performed several times on the same instruction.
The Pointer Register is used to store an address value specifying locations within the PDIBUS
address space. During direct data access, the Pointer Register is updated by the specified num-
ber of address bytes given as operand bytes to the instruction. During indirect data access,
addressing is based on an address already stored in the Pointer Register prior to the access
REPEAT
LDCS
STCS
LDS
STS
KEY
LD
ST
0
0
0
1
1
1
1
0
Cmd
Cmd
0
1
0
1
0
1
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
Size A
Ptr
CS Address
0
0
0
Size A/B
Size B
Size B
0
Cmd
0
0
0
0
1
1
1
1
Size A - Address size (direct access)
0
0
1
1 1
Ptr - Pointer access (indirect access)
0
0
1
1 1
Size B - Data size
0
0
1
1 1
CS Address (CS - Control/Status reg.)
0
0
0
0
1
0
0
1
1 1
0 0
0
1
1 1
0
1
0
0
1
0
0
1
0
0 0
0 0
0 1
0 1
1 1
0
1
0
1
0
Byte
Word (2 Bytes)
3 Bytes
Long (4 Bytes)
*(ptr)
*(ptr++)
ptr
ptr++ - Reserved
Byte
Word (2 Bytes)
3 Bytes
Long (4 Bytes)
LDS
LD
STS
ST
LDCS (LDS Control/Status)
REPEAT
STCS (STS Control/Status)
KEY
0
1
0
1
1
Register 0
Register 1
Register 2
Reserved
Reserved
......
XMEGA D
267
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