ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 99
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.7
10.8
10.8.1
10.8.2
8210B–AVR–04/10
Moving Interrupts Between Application and Boot Section
Register Description
STATUS - PMIC Status Register
INTPRI - PMIC Priority Register
The interrupt vectors can be moved from the default location in the Application Section in Flash
to the start of the Boot Section.
• Bit 7 - NMIEX: Non-Maskable Interrupt Executing
This flag is set if a Non-Maskable Interrupt is executing. The flag will be cleared when returning
(RETI) from the interrupt handler.
• Bit 6:3 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 2 - HILVLEX: High Level Interrupt Executing
This flag is set if a high level interrupt is executing or the interrupt handler has been interrupted
by an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
• Bit 1 - MEDLVLEX: Medium Level Interrupt Executing
This flag is set if a medium level interrupt is executing or the interrupt handler has been inter-
rupted by an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI)
from the interrupt handler.
• Bit 0 - LOLVLEX: Low Level Interrupt Executing
This flag is set if a low level interrupt is executing or the interrupt handler has been interrupted by
an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the
interrupt handler.
• Bit 7:0 - INTPRI: Interrupt Priority
When round-robin scheduling is enabled, this register stores the interrupt vector of the last
acknowledged low-level interrupt. The stored interrupt vector will have the lowest priority next
time one or more low-level interrupts are pending. The register is accessible from software to
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
NMIEX
R/W
R
7
0
7
0
R/W
R
6
–
0
6
0
R/W
R
5
–
0
5
0
R/W
R
4
–
0
4
0
INTPRI[7:0]
R/W
R
3
–
0
3
0
HILVLEX
R/W
R
2
0
2
0
MEDLVLEX
R/W
R
1
0
1
0
XMEGA D
LOLVLEX
R/W
R
0
0
0
0
STATUS
INTPRI
99
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