ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 175
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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CYPRESS
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101
Company:
Part Number:
ATxmega192D3-AU
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70
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Part Number:
ATxmega192D3-H
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SQ
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719
Company:
Part Number:
ATxmega192D3-MH
Manufacturer:
Atmel
Quantity:
565
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16.3.9
8210B–AVR–04/10
Synchronization
Figure 16-9. TWI Arbitration
Figure 16-9
devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to
transmit a high level (bit 5) while DEVICE2 is transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data
bit, or a repeated START condition and STOP condition are not allowed and will require special
handling by software.
A clock synchronization algorithm is necessary for solving situations where more than one mas-
ter is trying to control the SCL line at the same time. The algorithm is based on the same
principles used for clock stretching previously described.
two masters are competing for the control over the bus clock. The SCL line is the wired-AND
result of the two masters clock outputs.
Figure 16-10. Clock Synchronization
A high to low transition on the SCL line will force the line low for all masters on the bus and they
start timing their low clock period. The timing length of the low clock period can vary between the
masters. When a master (DEVICE1 in this case) has completed its low period it releases the
SCL line. However, the SCL line will not go high before all masters have released it. Conse-
quently the SCL line will be held low by the device with the longest low period (DEVICE2).
Devices with shorter low periods must insert a wait-state until the clock is released. All masters
start their high period when the SCL line is released by all devices and has become high. The
DEVICE1_SCL
DEVICE2_SCL
SCL
(wired-AND)
DEVICE1_SDA
DEVICE2_SDA
SDA
(wired-AND)
SCL
shows an example where two TWI masters are contending for bus ownership. Both
S
Low Period
Count
DEVICE1 Loses arbitration
bit 7
State
Wait
Figure 16-10
bit 6
High Period
Count
bit 5
shows an example where
XMEGA D
bit 4
175
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