ATxmega192D3 Atmel Corporation, ATxmega192D3 Datasheet - Page 185
ATxmega192D3
Manufacturer Part Number
ATxmega192D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega192D3
Flash (kbytes)
192 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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16.9.5
8210B–AVR–04/10
BAUD - TWI Baud Rate Register
• Bit 2 - BUSERR: Bus Error
The Bus Error (BUSERR) flag is set if an illegal bus condition has occurred. An illegal bus condi-
tion occurs if a Repeated START or STOP condition is detected, and the number of bits from the
previous START condition is not a multiple of nine. Writing a one to this bit location will clear the
BUSERR flag.
Writing the ADDR register will automatically clear the BUSERR flag.
• Bit 1:0 - BUSSTATE[1:0]: Bus State
The Bus State (BUSSTATE) bits indicate the current TWI bus state as defined in
The change of bus state is dependent on bus activity. Refer to the
Logic” on page
Table 16-5.
Writing 01 to the BUSSTATE bits forces the bus state logic into idle state. The bus state logic
cannot be forced into any other state. When the master is disabled, and after reset the Bus State
logic is disabled and the bus state is unknown.
The Baud Rate (BAUD) register defines the relation between the system clock and the TWI Bus
Clock (SCL) frequency. The frequency relation can be expressed by using the following
equation:
The BAUD register must be set to a value that results in a TWI bus clock frequency (f
or less 100 kHz or 400 kHz dependent on standard used by the application. The following equa-
tion [2] expresses equation [1] with respect to the BAUD value:
The BAUD register should be written while the master is disabled.
f
TWMBR
TWI
Bit
+0x04
Read/Write
Initial Value
=
BUSSTATE[1:0]
--------------------------------------- - [Hz]
2(5
=
+
------------- - 5
2f
00
01
10
11
f
TWMBR)
f
sys
TWI
sys
R/W
7
0
TWI master Bus State
176.
–
[2]
R/W
6
0
[1]
Group Configuration
UNKNOWN
R/W
5
0
OWNER
BUSY
IDLE
R/W
4
0
BAUD[7:0]
R/W
Description
Unknown Bus State
Idle
Owner
Busy
3
0
R/W
2
0
Section 16.4 ”TWI Bus State
R/W
1
0
XMEGA D
R/W
0
0
Table
TWI
) equal
BAUD
16-5.
185
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