ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 109

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.5
9.5.1
9.5.2
8077H–AVR–12/09
Register Description
STATUS - Reset Status Register
CTRL - Reset Control Register
• Bit 7 – 6: Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 5 – SRF: Software Reset Flag
This flag is set if a Software reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 4 - PDIRF: Program and Debug Interface Reset Flag
This flag is set if a Programming interface reset occurs. The flag will be cleared by a power-on
reset or by writing a one to the bit location.
• Bit 3 - WDRF: Watchdog Reset Flag
This flag is set if a Watchdog reset occurs. The flag will be cleared by a power-on reset or by
writing a one to the bit location.
• Bit 2 - BORF: Brown Out Reset Flag
This flag is set if a Brown out reset occurs. The flag will be cleared by a power-on reset or by
writing a one to the bit location.
• Bit 1 - EXTRF: External Reset Flag
This flag is set if an External reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 0 - PORF: Power On Reset Flag
This flag is set if a Power-on reset occurs. Writing a one to the flag will clear the bit location.
• Bit 7:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - SWRST: Software Reset
When this bit is set, a Software reset will occur. The bit is cleared when a reset is issued. This bit
is protected by the Configuration Change Protection, for details refer to
tion Change Protection” on page
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
R
7
–
0
R
7
–
-
R
6
–
0
6
–
R
-
SRF
R/W
R
5
–
0
12.
5
-
PDIRF
R/W
R
4
–
0
4
-
WDRF
R/W
R
3
–
0
3
-
BORF
R/W
R
2
–
0
2
-
EXTRF
R/W
Section 3.12 ”Configura-
1
–
R
0
1
-
XMEGA A
SWRST
PORF
R/W
R/W
0
0
0
-
STATUS
CTRL
109