ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 56

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.2
8077H–AVR–12/09
CTRLB - DMA Channel Control Register B
• Bit 2 - SINGLE: DMA Channel Single Shot Data transfer
Setting this bit enables the single shot mode. The channel will then do a burst transfer of
BURSTLEN bytes on the transfer trigger. This bit can not be changed if the channel is busy.
• Bit 1:0 - BURSTLEN[1:0]: DMA Channel Burst Mode
These bits decide the DMA channel burst mode according to
can not be changed if the channel is busy.
Table 5-3.
• Bit 7- CHBUSY - DMA Channel Busy
When the DMA Channel starts a DMA transaction, the CHBUSY flag will be read as one. This
flag is automatically cleared when the DMA channel is disabled, when the Channel Transaction
Complete Interrupt Flag is set or if the Channel Error Interrupt flag is set.
• Bit 6 - CHPEND - DMA Channel Pending
If a block transfer is pending on the DMA channel, the CHPEND flag will be read as one. This
flag is automatically cleared when the transfer starts, or if the transfer is aborted
• Bit 5 - ERRIF - DMA Channel Error Interrupt Flag
If an error condition is detected the DMA channel the ERRIF flag will be set, and the optional
interrupt is generated. Since the DMA Channel Error Interrupt share interrupt address with DMA
Channel Transaction Complete, the ERRIF will not be cleared when the interrupt vector is exe-
cuted. This flag is cleared by writing a one to the bit location.
• Bit 4 - TRNIF - DMA Channel n Transaction Complete Interrupt Flag
When a transaction on the DMA Channel has been completed, the TRNIF flag will set, and the
optional interrupt is generated. When repeat is not enabled the transaction is complete and the
TRNIFR is set after the block transfer. When unlimited repeat is enabled the TRNIF is also set
after each block transfer.
Since the DMA Channel Transaction Complete Channel Error Interrupt share interrupt address
with DMA Channel Error Interrupt, the TRNIF will not be cleared when the interrupt vector is exe-
cuted. This flag is cleared by writing a one to the bit location.
Bit
+0x04
Read/Write
Initial Value
BURSTLEN[1:0]
00
01
10
11
CHBUSY
DMA channel burst mode
R
7
0
CHPEND
6
R
0
ERRIF
R/W
5
0
Group Configuration
1BYTE
2BYTE
4BYTE
8BYTE
TRNIF
R/W
4
0
R/W
ERRINTLVL[1:0]
3
0
R/W
Table 5-3 on page
2
0
Description
1 byte burst mode
2 bytes burst mode
4 bytes burst mode
8 bytes burst mode
R/W
1
TRNINTLVL[1:0]
0
XMEGA A
R/W
56. These bits
0
0
CTRLB
56