ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 223

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10 Register Description - TWI Slave
19.10.1
19.10.2
8077H–AVR–12/09
CTRLA - TWI Slave Control Register A
CTRLB - TWI Slave Control Register B
• Bit 7:6 - INTLVL[1:0]: TWI Slave Interrupt Level
The Slave Interrupt Level (INTLVL) bits select the interrupt level for the TWI slave interrupts.
• Bit 5 - DIEN: Data Interrupt Enable
Setting the Data Interrupt Enable (DIEN) bit enables the Data Interrupt when the Data Interrupt
Flag (DIF) in the STATUS register is set. The INTLVL bits must be unequal zero for the interrupt
to be generated.
• Bit 4 - APIEN: Address/Stop Interrupt Enable
Setting the Address/Stop Interrupt Enable (APIEN) bit enables the Address/Stop Interrupt when
the Address/Stop Interrupt Flag (APIF) in the STATUS register is set. The INTLVL bits must be
unequal zero for interrupt to be generated.
• Bit 3 - ENABLE: Enable TWI Slave
Setting the Enable TWI Slave (ENABLE) bit enables the TWI slave.
• Bit 2 - PIEN: Stop Interrupt Enable
Setting the Stop Interrupt Enable (PIEN) bit will set the APIF in the STATUS register when a
STOP condition is detected.
• Bit 1 - PMEN: Promiscuous Mode Enable
By setting the Promiscuous Mode Enable (PMEN) bit, the slave address match logic responds to
all received addresses. If this bit is cleared, the address match logic uses the ADDR register to
determine which address to recognize as its own address.
• Bit 0 - SMEN: Smart Mode Enable
Setting the Smart Mode Enable (SMEN) bit enables Smart Mode. When Smart mode is enabled,
the Acknowledge Action, as set by the ACKACT bit in the CTRLB register, is sent immediately
after reading the DATA register.
• Bit 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
R/W
7
0
R
7
0
-
INTLVL[1:0]
R/W
6
0
R
6
0
-
DIEN
R/W
5
0
R
5
0
-
APIEN
R/W
4
0
R
4
0
-
ENABLE
R/W
3
0
3
R
0
-
ACKACT
PIEN
R/W
R/W
2
0
2
0
PMEN
R/W
R/W
1
0
1
0
CMD[1:0]
XMEGA A
SMEN
R/W
R/W
0
0
0
0
CTRLA
CTRLB
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