ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 285

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.12.2
8077H–AVR–12/09
CTRLB (SRAM) - Chip Select Control Register B
Table 24-17. Address space encoding (Continued)
1.
• Bit 1:0 - MODE[1:0]: Chip Select Mode
These bits select the Chip Select Mode and decide what type of interface is used for the external
memory or peripheral according to
Table 24-18. Chip Select Mode selection
1.
This configuration options in this register depend on the Chip Select Mode configuration. The
register description below is valid when the Chip Select Mode is configured for SRAM or SRAM
LPC.
• Bit 7:3 - Reserved
These bits are reserved and will always be read as zero.
• Bit 2:0 - SRWS[2:0]: SRAM Wait State
These bits select the number of wait states for SRAM and SRAM LPC access as a number of
Peripheral 2x clock (CLK
Table 24-19. Wait State selection
Bit
+0x01
Read/Write
Initial Value
ASIZE[5:0]
01111
10000
Other
MODE[1:0]
SRWS[2:0]
Entire available data space used.
SDRAM can only be selected for CS3
000
001
010
011
100
00
01
10
11
R/W
7
0
-
R/W
6
0
-
Group Configuration
8M
16M
Group Configuration
DISABLE
SRAM
LPC
SDRAM
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
PER2
) cycles, according to
R/W
5
0
-
Table 24-18 on page
R/W
4
0
-
Address Size
8M Bytes
16M
-
Description
Chip Select Disabled
Enable Chip Select for SRAM
Enable Chip Select for SRAM LPC
Enable Chip Select for SDRAM
Description
0 CLK
1 CLK
2 CLK
3 CLK
4 CLK
R/W
3
0
-
Table 24-19 on page
(1)
PER2
PER2
PER2
PER2
PER2
285.
cycles wait state
cycles wait state
cycles wait state
cycles wait state
cycles wait state
R/W
2
0
Address Lines Compared
ADDR[23]
-
Reserved
SRWS[2:0]
R/W
1
0
285.
R/W
(1)
0
0
XMEGA A
CTRLB
285