ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 297

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.9.1
25.9.2
8077H–AVR–12/09
Single conversion without gain
Single conversion with gain
RES is the resolution, 8- or 12-bit. The propagation delay will increase by one extra ADC clock
cycle if the Gain Stage (GAIN) is used.
Even though the propagation delay is longer than one ADC clock cycle, the pipelined design
removes any limitations on sample speed versus propagation delay.
Figure 25-13 on page 297
ing of the start conversion bit, or the event triggering the conversion (START), must occur
minimum one peripheral clock cycles before the ADC clock cycle where the conversion actually
start (indicated with the grey slope of the START trigger).
The analog input source is sampled in the first half of the first cycle, and the sample time is
always a half ADC clock period. Using a faster or slower ADC clock and sample rate will affect
the sample time.
The Most Significant Bit (MSB) of the result is converted first, and the rest of the bits are con-
verted during the next 3 (for 8-bit results) or 5 (for 12-bit results) ADC clock cycles. Converting
one bit takes a half ADC clock period. During the last cycle the result is prepared before the
Interrupt Flag is set. The result is available in the Result Register for readout.
Figure 25-13. ADC timing for one single conversion without gain
Figure 25-14 on page 298
the
the gainstage will sample and amplify the analog input source before the ADC samples an con-
verts the amplified analog value. Compared to a single conversion without gain this adds one
ADC clock cycle (between START and ADC Sample) for the gain stage sample and amplify. The
sample time for the gain stage is a half ADC clock cycle.
Propagation Delay =
CONVERTING BIT
”Overview” on page 289
ADC SAMPLE
CLK
START
ADC
IF
1
----------------------------------------- -
1
+
MSB
RES
---------- -
2
f
ADC
shows the ADC timing for one single conversion with gain. As seen in
shows the ADC timing for a single conversion without gain. The writ-
+
10
the gain stage is placed prior to the actual ADC. This means that
GAIN
2
9
8
3
7
6
4
5
4
5
3
2
6
1
LSB
XMEGA A
7
8
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