ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 82

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.8
8077H–AVR–12/09
External Clock Source Failure Monitor
Figure 7-6.
When the DFLL is enabled it will count each oscillator clock cycle, and for each reference clock
edge, the counter value is compared to the fixed ideal relationship between the reference clock
and the 1kHz reference frequency. If the internal oscillator runs too fast or too slow, the DFLL
will decrement or increment the corresponding DFLL Calibration Register value by one to adjust
the oscillator frequency slightly. When the DFLL is enabled the DFLL Calibration Register can-
not be written from software.
The ideal counter value representing the number of oscillator clock cycles for each reference
clock cycle is loaded to the DFLL Oscillator Compare Register during reset. The register can
also be written from software to change the frequency the internal oscillator is calibrated to.
The DFLL will stop when entering a sleep-mode where the oscillators are stopped. After wake-
up the DFLL will continue with the calibration value found before entering sleep. For the DFLL
Calibration Register to be reloaded with the default value it has after reset, the DFLL must dis-
abled before entering sleep and enabled the again after leaving sleep.
The active reference cannot be disabled when the DFLL is enabled.
When the DFLL is disabled the DFLL calibration Register can be written from software for man-
ual run-time calibration of the oscillator.
For details on internal oscillator accuracy when the DFLL is enabled, refer to the device data
sheet.
To handle external clock source failures, there is a built-in monitor circuit monitoring the oscilla-
tor or clock used to derive the XOSC clock. The External Clock Source Failure Monitor is
disabled by default, and it must be enabled from software before it can be used. If an external
TOSC1
TOSC2
Figure 5-5. DFLL reference clock selection
32.768 kHz Crystal Osc.
32.768 kHz Int. Osc.
32 MHz Int. Osc.
2 MHz Int. Osc.
DFLL
DFLL
XMEGA A
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