ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 64

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.15
5.16
5.17
Table 5-13.
8077H–AVR–12/09
Address
Address
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x10
+0x20
+0x30
+0x40
+0x0A
+0x0B
+0x0C
+0x0D
+0x0E
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x07
+0x08
+0x09
+0x0F
Offset
0x00
0x02
0x04
0x06
Register Summary – DMA Controller
Register Summary – DMA Channel
DMA Interrupt Vector Summary
Name
Name
DESTADDR0
DESTADDR1
DESTADDR2
SRCADDR0
SRCADDR1
SRCADDR2
INTFLAGS
CH0 Offset
CH1 Offset
CH2 Offset
CH3 Offset
DMA Interrupt vectors and their word offset addresses from the DMA Controller interrupt base
ADDCTRL
TRFCNTH
Reserved
Reserved
Reserved
TRIGSRC
TRFCNTL
Reserved
Reserved
Reserved
STATUS
REPCNT
TEMPH
TEMPL
CTRLA
CTRLB
CTRL
CH3ERRIF
CH3BUSY
CH0_vect
CH1_vect
CH2_vect
CH3_vect
ENABLE
CHBUSY
Source
Bit 7
Bit 7
CHEN
-
-
-
-
-
-
SRCRELOAD[1:0]
CH2ERRIF
CH2BUSY
CHPEND
RESET
CHRST
Bit 6
Bit 6
-
-
-
-
-
-
Interrupt Description
DMA Controller Channel 0 Interrupt vector
DMA Controller Channel 1 Interrupt vector
DMA Controller Channel 2 Interrupt vector
DMA Controller Channel 3 Interrupt vector
CH1ERRIF
CH1BUSY
REPEAT
Bit 5
Bit 5
ERRIF
-
-
-
-
-
-
-
SRCDIR[1:0]
Offset address for DMA Channel 0
Offset address for DMA Channel 0
Offset address for DMA Channel 0
Offset address for DMA Channel 0
CH0ERRIF
CH0BUSY
TRFREQ
Bit 4
TRNIF
Bit 4
-
-
-
-
-
-
-
DESTADDR[23:16]
SRCADDR[23:16]
DESTADDR[15:8]
SRCADDR[15:8]
DESTADDR[7:0]
SRCADDR[7:0]
TRIGSRC[7:0]
TRFCNT[15:8]
TRFCNT[7:0]
REPCNT[7:0]
TEMP[15:8]
TEMP[7:0]
CH3TRNFIF
CH3PEND
Bit 3
Bit 3
DESTRELOAD[1:0]
-
-
-
-
-
-
-
DBUFMODE[1:0]
ERRINTLVL[1:0]
CH2TRNFIF
CH2PEND
SINGLE
Bit 2
Bit 2
-
-
-
-
-
-
CH1TRNFIF
CH1PEND
Bit 1
Bit 1
-
-
-
-
-
-
TRNINTLVL[1:0]
PRIMODE[1:0]
DESTDIR[1:0]
BURSTLEN
CH0TRNFIF
CH0PEND
XMEGA A
Bit 0
Bit 0
-
-
-
-
-
-
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