SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 150

• Manufacturer Part Number: SAM3N2A
• Manufacturer: Atmel Corporation

Specifications of SAM3N2A

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.19 About the
150
SAM3N
Cortex-M3
The address map of the Private peripheral bus (PPB) is:
Table 10-26. Core peripheral register regions
1.
In register descriptions:
Address
0xE000E008-
0xE000E00F
0xE000E010-
0xE000E01F
0xE000E100-
0xE000E4EF
0xE000ED00-
0xE000ED3F
0xE000ED90-
0xE000ED93
0xE000EF00-
0xE000EF03
• the register type is described as follows:
• the required privilege gives the privilege level required to access the register, as follows:
RW
RO
WO
Privileged
Unprivileged
Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a memory
peripherals
protection unit (MPU).
Read and write.
Read-only.
Write-only.
Core peripheral
System control block
System timer
Nested Vectored Interrupt
Controller
System control block
MPU Type Register
Nested Vectored Interrupt
Controller
Only privileged software can access the register.
Both unprivileged and privileged software can access the register.
Description
Table 10-30 on page 164
Table 10-33 on page 191
Table 10-27 on page 151
Table 10-30 on page 164
Reads as zero, indicating no MPU is
implemented
Table 10-27 on page 151
(1)
11011A–ATARM–04-Oct-10