SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 474

• Manufacturer Part Number: SAM3N2A
• Manufacturer: Atmel Corporation

Specifications of SAM3N2A

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.8.10
Figure 28-15. TWI Write Operation with Single Data Byte without Internal Address
474
474
SAM3N
SAM3N
Read-write Flowcharts
The following flowcharts shown in
28-18 on page
read and write operations. A polling or interrupt method can be used to check the status bits.
The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
477,
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Device slave address (DADR)
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Figure 28-19 on page 478
Write ==> bit MREAD = 0
TWI_THR = Data to send
Set the Control register:
Write STOP Command
Load Transmit register
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
TWI_CR = STOP
Transfer finished
- Master enable
TXCOMP = 1?
Set TWI clock
TXRDY = 1?
Yes
Yes
BEGIN
Figure 28-16 on page
and
No
No
Figure 28-20 on page 479
475,
Figure 28-17 on page
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
give examples for
476,
Figure