SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 159

• Manufacturer Part Number: SAM3N2A
• Manufacturer: Atmel Corporation

Specifications of SAM3N2A

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.20.7.4
10.20.7.5
10.20.7.6
• Priority, byte offset 3
• Priority, byte offset 2
• Priority, byte offset 1
• Priority, byte offset 0
Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
See
interrupt priority array, that provides the software view of the interrupt priorities.
11011A–ATARM–04-Oct-10
“The CMSIS mapping of the Cortex-M3 NVIC registers” on page 151
31
23
15
31
23
15
31
23
15
7
7
7
IPR2
IPR1
IPR0
30
22
14
30
22
14
30
22
14
6
6
6
29
21
13
29
21
13
29
21
13
5
5
5
28
20
12
28
20
12
28
20
12
4
4
4
IP[11]
IP[10]
IP[9]
IP[8]
IP[6]
IP[5]
IP[4]
IP[3]
IP[2]
IP[1]
IP[0]
27
19
11
27
19
11
27
19
11
3
3
3
for more information about the IP[0] to IP[32]
26
18
10
26
18
10
26
18
10
2
2
2
25
17
25
17
25
17
9
1
9
1
9
1
SAM3N
24
16
24
16
24
16
8
0
8
0
8
0
159