SAM7X512 Atmel Corporation, SAM7X512 Datasheet - Page 667

• Manufacturer Part Number: SAM7X512
• Manufacturer: Atmel Corporation

Specifications of SAM7X512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.6.6
41.6.6.1
41.6.7
41.6.7.1
6120I–ATARM–06-Apr-11
Serial Peripheral Interface (SPI)
Universal Synchronous Asynchronous Receiver Transmitter (USART)
SPI: Bad Serial Clock Generation on 2nd Chip Select
USART: DCD is Active High instead of Low
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Add an inverter.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
SAM7X512/256/128
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