SAM7X512 Atmel Corporation, SAM7X512 Datasheet - Page 665

• Manufacturer Part Number: SAM7X512
• Manufacturer: Atmel Corporation

Specifications of SAM7X512

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.6
41.6.1
41.6.1.1
41.6.2
41.6.2.1
41.6.2.2
41.6.3
41.6.3.1
6120I–ATARM–06-Apr-11
AT91SAM7X256/128 Errata - Rev. C Parts
Embedded Flash Controller (EFC)
Ethernet MAC (EMAC)
Peripheral Input/Output (PIO)
EFC: Embedded Flash Access Time 2
EMAC: Possible Event Loss when Reading EMAC_ISR
EMAC: Possible Event Loss when Reading the Statistics Register Block
PIO: Electrical Characteristics on NRST, PA0-PA30 and PB0-PB26
Refer to
Note:
The embedded Flash maximum access time is 20 MHz (instead of 30 MHz at zero Wait State
(FWS = 0).
The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55
MHz). Above 48.1 MHz and up to 55MHz, two Wait States (FWS = 2) are required.
Set the number of Wait States (FWS) according to the frequency requirements described in this
errata.
If an event occurs within the same clock cycle in which the EMAC_ISR is read, the correspond-
ing bit might be cleared even though it has not been read at 1. This might lead to the loss of this
event.
Each time the software reads EMAC_ISR, it has to check the contents of the Transmit Status
Register (EMAC_TSR), the Receive Status Register (EMAC_RSR) and the Network Status
Register (EMAC_NSR), as the possible lost event is still notified in one of these registers.
If an event occurs within the same clock cycle during which a statistics register is read, the cor-
responding counter might lose this event. This might lead to the loss of the incrementation of
one for this counter.
None
When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, the volt-
age of the I/O stabilizes at VPull-up.
Vpull-up
VPull-up Min
VDDIO - 0.65 V
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM7X256 Revision C chip ID is 0x275B 0942.
AT91SAM7X128 Revision C chip ID is 0x275A 0742.
Section 41.1 “Marking” on page
VPull-up Max
VDDIO - 0.45 V
635.
SAM7X512/256/128
665