SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 1189

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 45-39. SSC Timings
Notes:
11052C–ATARM–21-Nov-11
Symbol
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1)
(1)
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
3. 1.8V domain: V
4. 3.3V domain: V
(Receive Start Selection), two Periods of the MCK must be added to timings.
RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabilization.
45-20
Parameter
TK edge to TF/TD (TK output, TF output)
TK edge to TF/TD (TK input, TF output)
TF setup time before TK edge (TK output)
TF hold time after TK edge (TK output)
TK edge to TD (TK output, TF input)
TF setup time before TK edge (TK input)
TF hold time after TK edge (TK input)
TK edge to TD (TK input, TF input)
RF/RD setup time before RK edge (RK input)
RF/RD hold time after RK edge (RK input)
RK edge to RF (RK input)
RF/RD setup time before RK edge (RK output)
RF/RD hold time after RK edge (RK output)
RK edge to RF (RK output)
illustrates Min and Max accesses for SSC0. The same applies to SSC1, SSC4, and SSC7, SSC10 and SSC13.
VDDIO
VDDIO
from 1.65V to 1.95V, maximum external capacitor = 20pF.
from 3.0V to 3.6V, maximum external capacitor = 30pF.
Transmitter
Cond
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
Receiver
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
-5.6 (+2*t
-4.6 (+2*t
3.0 (+3*t
2.3 (+3*t
14.1 - t
10.0 - t
t
t
CPMCK
CPMCK
t
t
CPMCK
CPMCK
14.0
Min
-5.6
-4.6
-5.9
-4.9
3.0
2.3
9.9
2.6
2.0
CPMCK
CPMCK
0
0
0
0
CPMCK
CPMCK
CPMCK
CPMCK
- 2.5
- 1.8
)
)
)
)
(1)(4)
(1)(4)
(1)(4)
(1)(4)
15.5(+3*t
11.1(+3*t
5.7 (+2*t
4.7 (+2*t
Max
15.7
11.4
15.2
10.9
5.8
4.9
5.2
4.3
CPMCK
CPMCK
CPMCK
CPMCK
SAM9G15
)
)
)
)
(1)(4)
(1)(4)
(1)(4)
(1)(4)
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1189