SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 1206

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

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SAM9G15
SAM9G15
30 DDR SDR SDRAM Controller (DDRSDRC) ......................................... 421
31 DMA Controller (DMAC) ...................................................................... 469
32 USB High Speed Device Port (UDPHS) .............................................. 527
29.3 I/O Lines Description ........................................................................................376
29.4 Multiplexed Signals ..........................................................................................376
29.5 Application Example .........................................................................................377
29.6 Product Dependencies .....................................................................................377
29.7 External Memory Mapping ...............................................................................378
29.8 Connection to External Devices .......................................................................378
29.9 Standard Read and Write Protocols .................................................................383
29.10 Automatic Wait States ....................................................................................391
29.11 Data Float Wait States ...................................................................................395
29.12 External Wait ..................................................................................................399
29.13 Slow Clock Mode ............................................................................................405
29.14 Asynchronous Page Mode .............................................................................408
29.15 Programmable IO Delays ...............................................................................411
29.16 Static Memory Controller (SMC) User Interface .............................................412
30.1 Description .......................................................................................................421
30.2 Embedded Characteristics ...............................................................................421
30.3 DDRSDRC Module Diagram ............................................................................423
30.4 Initialization Sequence .....................................................................................424
30.5 Functional Description ......................................................................................429
30.6 Software Interface/SDRAM Organization, Address Mapping ...........................447
30.7 DDR SDR SDRAM Controller (DDRSDRC) User Interface ..............................451
31.1 Description .......................................................................................................469
31.2 Embedded Characteristics ...............................................................................469
31.3 Block Diagram ..................................................................................................472
31.4 Functional Description ......................................................................................473
31.5 DMAC Software Requirements ........................................................................500
31.6 Write Protection Registers ................................................................................501
31.7 DMA Controller (DMAC) User Interface ...........................................................502
32.1 Description .......................................................................................................527
32.2 Embedded Characteristics ...............................................................................527
32.3 Block Diagram ..................................................................................................529
32.4 Typical Connection ...........................................................................................530
11052C–ATARM–21-Nov-11
11052C–ATARM–21-Nov-11