SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 911

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.5
42.6
42.6.1
42.6.2
42.6.3
11052C–ATARM–21-Nov-11
Pin Name List
Product Dependencies
I/O Lines
Power Management
Interrupt
Table 42-1.
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
Table 42-2.
The SSC is not continuously clocked. The SSC interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the SSC clock.
The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling interrupts requires programming the AICbefore configuring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each
Table 42-3.
pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt ser-
vice routine can get the interrupt origin by reading the SSC interrupt status register.
Pin Name
RF
RK
RD
TF
TK
TD
Instance
Instance
SSC
SSC
SSC
SSC
SSC
SSC
SSC
I/O Lines Description
I/O Lines
Peripheral IDs
Pin Description
Receiver Frame Synchro
Receiver Clock
Receiver Data
Transmitter Frame Synchro
Transmitter Clock
Transmitter Data
28
ID
Signal
RD
RF
RK
TD
TK
TF
I/O Line
PA27
PA29
PA28
PA26
PA25
PA24
SAM9G15
Input/Output
Input/Output
Input/Output
Input/Output
Output
Type
Input
Peripheral
B
B
B
B
B
B
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