SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 689
SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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35.8.9
Name:
Address:
Access:
Note:
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
• BITS: Bits Per Transfer
(See the
The BITS field determines the number of data bits transferred. Reserved values should not be used.
11052C–ATARM–21-Nov-11
Value
31
23
15
7
SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans-
lated value unless the register is written.
0
1
2
3
4
5
6
(Note:)
SPI Chip Select Register
below the register table;
Name
8_BIT
9_BIT
10_BIT
11_BIT
12_BIT
13_BIT
14_BIT
30
22
14
SPI_CSRx[x=0..3]
0xF0000030 (0), 0xF0004030 (1)
Read/Write
6
BITS
29
21
13
5
Section 35.8.9 “SPI Chip Select Register” on page
Description
8 bits for transfer
9 bits for transfer
10 bits for transfer
11 bits for transfer
12 bits for transfer
13 bits for transfer
14 bits for transfer
28
20
12
4
DLYBCT
DLYBS
SCBR
CSAAT
27
19
11
3
26
18
10
–
2
689.)
NCPHA
25
17
9
1
SAM9G15
CPOL
24
16
8
0
689
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