SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 665

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SAM9G15

Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G15

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
35.4
Figure 35-2. Application Block Diagram: Single Master/Multiple Slave Implementation
35.5
Table 35-1.
35.6
35.6.1
35.6.2
11052C–ATARM–21-Nov-11
Pin Name
MISO
MOSI
SPCK
NPCS1-NPCS3
NPCS0/NSS
Application Block Diagram
Signal Description
Product Dependencies
I/O Lines
Power Management
Signal Description
SPI Master
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the SPI pins to their peripheral
functions.
The SPI may be clocked through the Power Management Controller (PMC), thus the program-
mer must first configure the PMC to enable the SPI clock.
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
NPCS3
Pin Description
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select/Slave Select
NC
SPCK
MISO
MOSI
NSS
SPCK
MISO
MOSI
NSS
SPCK
MISO
MOSI
NSS
Master
Input
Output
Output
Output
Output
Slave 0
Slave 1
Slave 2
Type
SAM9G15
Slave
Output
Input
Input
Unused
Input
665

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