SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 146
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SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Instruction Cycle Timings
6.2
6-4
Branch and branch with link
A branch instruction calculates the branch destination in the first cycle, while
performing a prefetch from the current PC. This prefetch is done in all cases because,
by the time the decision to take the branch has been reached, it is already too late to
prevent the prefetch.
During the second cycle a fetch is performed from the branch destination, and the return
address is stored in register 14 if the link bit is set.
The third cycle performs a fetch from the destination +L, refilling the instruction
pipeline. If the instruction is a branch with link (R14 is modified) four is subtracted from
R14 to simplify the return instruction from
subroutines to push R14 onto the stack and pop directly into PC upon completion.
The cycle timings are listed in Table 6-1 where:
•
•
•
Branch with link is not available in Thumb state.
pc is the address of the branch instruction
alu is the destination address calculated by the ARM7TDMI core
(alu) is the contents of that address.
Cycle
1
2
3
Note
Copyright © 1994-2001. All rights reserved.
Address
pc+2L
alu
alu+L
alu+2L
MAS[1:0]
i
i
i
Table 6-1 Branch instruction cycle operations
0
0
0
nRW
Data
(pc+2L)
(alu)
(alu+L)
nMREQ
0
0
0
SEQ
0
1
1
ARM DDI 0029G
. This allows
nOPC
0
0
0
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