SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 149
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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6.5
ARM DDI 0029G
Data operations
A data operation executes in a single datapath cycle unless a shift is determined by the
contents of a register. A register is read onto the A bus, and a second register or the
immediate field onto the B bus (see Figure 1-3 on page 1-8). The ALU combines the A
bus source and the shifted B bus source according to the operation specified in the
instruction, and the result, when required, is written to the destination register.
Compare and test operations do not produce results. Only the ALU status flags are
affected.
An instruction prefetch occurs at the same time as the data operation, and the program
counter is incremented.
When the shift length is specified by a register, an additional datapath cycle occurs
during this cycle. The data operation occurs on the next cycle which is an internal cycle
that does not access memory. This internal cycle can be merged with the following
sequential access by the memory manager as the address remains stable through both
cycles.
The PC can be one or more of the register operands. When it is the destination, external
bus activity can be affected. If the result is written to the PC, the contents of the
instruction pipeline are invalidated, and the address for the next instruction prefetch is
taken from the ALU rather than the address incrementer. The instruction pipeline is
refilled before any further execution takes place, and during this time exceptions are
ignored.
PSR transfer operations (MSR and MRS) exhibit the same timing characteristics as the
data operations except that the PC is never used as a source or destination register.
The cycle timings are listed in Table 6-4 on page 6-8 where:
•
•
•
pc is the address of the branch instruction
alu is the destination address calculated by the ARM7TDMI core
(alu) is the contents of that address.
Note
Copyright © 1994-2001. All rights reserved.
Instruction Cycle Timings
6-7
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