AD6654 Analog Devices, AD6654 Datasheet - Page 11

• Manufacturer Part Number: AD6654
• Description: 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
• Manufacturer: Analog Devices

Specifications of AD6654

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 92.16MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Adc Architecture: Subranging
• Pkg Type: BGA,CSP

SERIAL PORT TIMING CHARACTERISTICS
Table 9.
Parameter
SERIAL PORT CLOCK TIMING REQUIREMENTS
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
1
2
3
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V and 3.6 V.
C
SCLK rise/fall time should be 3 ns maximum.
LOAD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCLK
SCLKL
SCLKH
SSDI
HSDI
SSCS
HSCS
DSDO
SSDI
HSDI
SSRFS
HSRFS
SSTFS
HSTFS
SSCS
HSCS
DSDO
= 40 pF on all outputs, unless otherwise noted.
1, 2, 3
SCLK Period
SCLK Low Time
SCLK High Time
SDI to ↑SCLK Setup Time
SDI to ↑SCLK Hold Time
SCS to ↑SCLK Setup Time
SCS to ↑SCLK Hold Time
↑SCLK to SDO Delay Time
SDI to ↑SCLK Setup Time
SDI to ↑SCLK Hold Time
SRFS to ↓SCLK Setup Time
SRFS to ↓SCLK Hold Time
STFS to ↓SCLK Setup Time
STFS to ↓SCLK Hold Time
SCS to ↑SCLK Setup Time
SCS to ↑SCLK Hold Time
↑SCLK to SDO Delay Time
Rev. 0 | Page 11 of 88
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
10.0
1.60
1.60
1.30
0.40
4.12
−2.78
4.28
0.80
0.40
1.60
−0.13
1.60
−0.30
4.12
−2.76
4.29
Typ
0.5 × t
0.5 × t
SCLK
SCLK
7.95
Max
7.96
AD6654
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns