AD6654 Analog Devices, AD6654 Datasheet - Page 62

• Manufacturer Part Number: AD6654
• Description: 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
• Manufacturer: Analog Devices

Specifications of AD6654

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 92.16MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Adc Architecture: Subranging
• Pkg Type: BGA,CSP

AD6654
SPI MODE TIMING
In SPI mode, the SCLK should run only when data is being
transferred and SCS is logic low. If SCLK runs when SCS is logic
high, the internal shift register continues to run and instruction
words or data are lost. No external framing is necessary. The
SCS pin can be pulled low once for each byte of transfer, or kept
low for the whole length of the transfer.
MSBFIRST
MSBFIRST
SMODE
MODE
MODE
SCLK
SDO
SCS
SDO
SCS
SDI
SDI
A7
A6
Figure 64. Serial Read of Three Bytes with MSBFIRST = 0 (All Words are Written or Read LSB First)
A5
BLOCK END ADDRESS
A4
BLOCK START
ADDRESS
A3
0xaa
A2
A1
A0
RD + COUNT (3)
Figure 65. SPI Write MSBFIRST = 1
0x83
WRITE
0
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N6
N5
DATA FROM BLOCK START
BLOCK COUNT (Nx)
N4
ADDRESS
aa
SPI Write
Data on the SDI pin is registered on the rising edge of SCLK.
During a write, the serial port accumulates eight input bits
of data before transferring one byte to the internal registers.
Figure 65 and Figure 66 show one byte block transfer for
writing in MSBFIRST and LSBFIRST modes.
N3
N2
N1
DATA FROM BLOCK START
ADDRESS + 1
N0
aa + 1
D7
D6
DATA FROM BLOCK START
ADDRESS + 2
D5
aa + 2
D4
D3
D2
D1
D0