AD6654 Analog Devices, AD6654 Datasheet - Page 64

• Manufacturer Part Number: AD6654
• Description: 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
• Manufacturer: Analog Devices

Specifications of AD6654

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 92.16MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Adc Architecture: Subranging
• Pkg Type: BGA,CSP

AD6654
MSBFIRST
SPORT MODE TIMING
In SPORT mode, the SCLK continuously runs, and the external
SRFS and STFS signals are used to frame the data. Incoming
framing signals SRFS (receive) and STFS (transmit) are sampled
on the falling edges of SCLK. All input and output data must be
transmitted or received in 8-bit segments starting with the
rising edge after SRFS or STFS is sampled.
MSBFIRST
SMODE
MODE
SMODE
SCLK
MODE
SDO
SCS
SCLK
SRFS
STFS
SDI
SDO
SCS
SDI
A0
A7
A1
A6
BLOCK START ADDRESS
BLOCK START ADDRESS
A2
A5
A3
A4
A4
A3
A5
A2
A6
A1
A7
A0
Figure 69. SPORT Write MSBFIRST = 1
Figure 68. SPI Read MSBFIRST = 0
WRITE
N0
0
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N6
N1
BLOCK COUNT (Nx)
N5
N2
BLOCK COUNT (Nx)
N4
N3
SPORT Write
Serial data is sampled on the rising edge of SCLK. The data
should be MSB or LSB first, depending on the polarity of the
MSBFIRST pin. The serial port begins to sample data on the
rising edge of SCLK after SRFS is detected on the falling edge of
SCLK. Once all 8-bits of one byte are shifted in, the data is
transferred to the internal bus.
N3
N4
N2
N5
N1
N6
READ
N0
1
D7
D0
D6
D1
D5
D2
D4
D3
D3
D4
D2
D5
D1
D6
D0
D7