AD6654 Analog Devices, AD6654 Datasheet - Page 48

• Manufacturer Part Number: AD6654
• Description: 14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
• Manufacturer: Analog Devices

Specifications of AD6654

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 92.16MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Adc Architecture: Subranging
• Pkg Type: BGA,CSP

AD6654
OUTPUT DATA ROUTER
The output data router circuit precedes the six AGCs of the
final output block and immediately follows interpolating half-
band filters. This block consists of two subblocks. The first
block is responsible for combining (interleaving) data from
more than one channel into a single stream of data. The second
block performs complex filter completion, as explained later in
this section. The combined data is passed on to the AGCs.
INTERLEAVING DATA
In some cases, filtering using a single channel is insufficient. For
such setups, it is advantageous to combine the filtering
resources of multiple channels rather than using filtering
resources from a single channel.
Multiple channels can be set up to co-process the ADC input
port data with the same NCO and filter setups. The decimation
phase values in one of the RCF filters are set such that the
channel’s filters are exactly out of phase with each other. In the
data router, these multiple channels are interleaved (combined)
to form a single stream of data. Because each individual channel
is decimated more than it would have been if a single channel
were filtering, more number-of-filter taps can be calculated.
This is best illustrated with an example:
Two channels need to work together to produce a filter at an
output rate of 9.216 MHz, when the input rate is 92.16 MHz.
Each channel is decimated by a factor of 20 (total decimation)
to achieve the desired output rate of 4.608 MHz each. This
compares to a decimation of 10, if a single channel were
working towards filtering.
CH0
CH1
CH2
CH3
CH4
CH5
Figure 55. Block Diagram of the Output Data Router
CONTROL
STREAM
AGC0
AGC1
AGC2
AGC3
AGC4
AGC5
AGC0
AGC1
AGC2
AGC3
AGC4
AGC5
PARALLEL
PARALLEL
PARALLEL
PORT A
PORT B
PORT C
Rev. 0 | Page 48 of 88
The same coefficients are programmed into both of the
channels’ RCF filters, and the decimation phases are set to 0
and 1. The decimation phases can be set to 0 for one channel
and 1 for the second channel in the pair. This causes the first
channel to produce the even outputs of the filter, and the
second to produce the odd outputs of the filter. The streams
are then recombined (interleaved) to produce the desired
9.216 MHz output rate. The benefit is that now each channel’s
RCF has time to calculate twice as many taps, because it has a
lower output rate.
The interleaving function is a simple time-multiplexing func-
tion, with lower data rate on the input side and higher data rate
on the output side. The output data rate is the sum of all input
stream data rates that are combined.
The channels that need to be combined are programmable with
sufficient flexibility. Table 24 gives the combinations that are
possible using a 4-bit word (stream control bits) in the Parallel
Port Control 2 register.
Table 24. Stream Control Bit Combinations and Selections
Stream
Control Bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Any other
state
Output Streams
Ch 0, Ch 1 combined; Ch 2, Ch 3,
Ch 4, Ch 5 independent
Ch 0, Ch 1, Ch 2 combined; Ch 3,
Ch 4, Ch 5 independent
Ch 0, Ch 1, Ch 2, Ch 3 combined;
Ch 4, Ch 5 independent
Ch 0, Ch 1, Ch 2, Ch 3, Ch 4
combined; Ch 5 independent
Ch 0, Ch 1, Ch 2, Ch 3, Ch 4, Ch 5
combined
Ch 0, Ch 1, Ch 2 combined; Ch 3,
Ch 4, Ch 5 combined
Ch 0, Ch 1 combined; Ch 2, Ch 3
combined; Ch 4, Ch 5 combined
Ch 0, Ch 1 combined; Ch 2, Ch 3
combined; Ch 4, Ch 5 independent
Ch 0, Ch 1, Ch 2 combined; Ch 3,
Ch 4 combined; Ch 5 independent
Ch 0, Ch 1, Ch 2, Ch 3 combined;
Ch 4, Ch 5 combined
Independent channels
Number of
Streams
5
4
3
2
1
2
3
3
3
2
6