AD6654 Analog Devices, AD6654 Datasheet - Page 55
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AD6654
Manufacturer Part Number
AD6654
Description
14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
Manufacturer
Analog Devices
Datasheet
1.AD6654.pdf
(88 pages)
Specifications of AD6654
Resolution (bits)
14bit
# Chan
1
Sample Rate
92.16MSPS
Interface
Par
Analog Input Type
Diff-Uni
Adc Architecture
Subranging
Pkg Type
BGA,CSP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD6654BBC
Manufacturer:
AD
Quantity:
13 888
Company:
Part Number:
AD6654BBC
Manufacturer:
ADI
Quantity:
280
Company:
Part Number:
AD6654BBC
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD6654BBC
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD6654BBCZ
Manufacturer:
ADI
Quantity:
853
Company:
Part Number:
AD6654BBCZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
AD6654CBC
Manufacturer:
ADI
Quantity:
283
Company:
Part Number:
AD6654CBC
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD6654CBC
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD6654CBCZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD6654CBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD6654XBC
Manufacturer:
ADI
Quantity:
284
Part Number:
AD6654XBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
MASTER/SLAVE PCLK MODES
The parallel ports can operate in either master or slave mode.
The mode is set via PCLK master mode bit in the Parallel Port
Control 2 register. The parallel ports power up in slave mode to
avoid possible contentions on the PCLK pin.
In master mode, PCLK is an output derived by dividing
PLL_CLK down by the PCLK divisor. The PCLK divisor can
have a value of 1, 2, 4, or 8, depending on the 2-bit PCLK
divisor word setting in the Parallel Port Control 2 register. The
highest PLCK rate in master mode is 200 MHz. Master mode is
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
Figure 60. Parallel I/Q Mode with an AGC Gain Word
t
DPREQ
Rev. 0 | Page 55 of 88
t
t
t
DPP
DPIQ
Q [15:8]
DPCH
I [15:8]
selected by setting the PCLK master mode bit in the Parallel
Port Control 2 register.
In slave mode, external circuitry provides the PCLK signal.
Slave mode PCLK signals can be either synchronous or
asynchronous. The maximum slave mode PCLK frequency is
also 200 MHz.
PxCH [2:0] = CHANNEL #
PCLK
rate
GAIN [11:0]
t
DPGAIN
0000 +
=
PLL
PCLK
_
CLK
divisor
rate
AD6654