AD6654 Analog Devices, AD6654 Datasheet - Page 65
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AD6654
Manufacturer Part Number
AD6654
Description
14-Bit, 92.16 MSPS, 4 & 6-Channel Wideband IF to Base Band Receiver
Manufacturer
Analog Devices
Datasheet
1.AD6654.pdf
(88 pages)
Specifications of AD6654
Resolution (bits)
14bit
# Chan
1
Sample Rate
92.16MSPS
Interface
Par
Analog Input Type
Diff-Uni
Adc Architecture
Subranging
Pkg Type
BGA,CSP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD6654BBC
Manufacturer:
AD
Quantity:
13 888
Company:
Part Number:
AD6654BBC
Manufacturer:
ADI
Quantity:
280
Company:
Part Number:
AD6654BBC
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD6654BBC
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD6654BBCZ
Manufacturer:
ADI
Quantity:
853
Company:
Part Number:
AD6654BBCZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
AD6654CBC
Manufacturer:
ADI
Quantity:
283
Company:
Part Number:
AD6654CBC
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD6654CBC
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD6654CBCZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD6654CBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD6654XBC
Manufacturer:
ADI
Quantity:
284
Part Number:
AD6654XBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
MSBFIRST
MSBFIRST
SPORT Read
For a typical SPORT read operation, the user must write an
address byte and instruction byte to the serial port to instruct
the internal control logic as to which registers are to be
SMODE
SMODE
MODE
MODE
SCLK
SCLK
SRFS
SRFS
STFS
STFS
SDO
SDO
SCS
SCS
SDI
SDI
A7
A0
A6
A1
BLOCK START ADDRESS
A5
BLOCK START ADDRESS
A2
A4
A3
A3
A4
A2
A5
A1
A6
A0
A7
Figure 70. SPORT Write MSBFIRST = 0
Figure 71. SPORT Read MSBFIRST = 1
READ
1
N0
Rev. 0 | Page 65 of 88
N6
N1
BLOCK COUNT (Nx)
N5
N2
BLOCK COUNT (Nx)
N4
N3
N3
readback. STFS must be asserted for every 8-bit readback and is
sampled on the falling edge of SCLK. Data is shifted out on the
rising edge of SCLK. The SDO pin is in a high impedance state
at all times except during a read operation.
N4
N2
N5
N1
N6
N0
WRITE
0
D7
D0
D6
D1
D5
D2
D4
D3
D3
D4
D2
D5
D1
D6
D0
D7
AD6654