ST7263BK1 STMicroelectronics, ST7263BK1 Datasheet - Page 118

• Manufacturer Part Number: ST7263BK1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BK1

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

On-chip peripherals
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2 ACK Acknowledge enable.
1 STOP Generation of a Stop condition.
0 ITE Interrupt enable.
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
This bit is set and cleared by software. It is also cleared by hardware in master
mode. Note: This bit is not cleared when the interface is disabled (PE=0).
In Master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition
is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In Slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this
mode the STOP bit has to be cleared by software.
This bit is set and cleared by software and cleared by hardware when the interface
is disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
SCL is held low when the SB, BTF or ADSL flags or an EV6 event (See
is detected.
Figure 49
Doc ID 7516 Rev 8
for the relationship between the events and the interrupt.
ST7263Bxx
Figure
48)