ST7263BK1 STMicroelectronics, ST7263BK1 Datasheet - Page 181

• Manufacturer Part Number: ST7263BK1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BK1

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

ST7263Bxx
16
16.1
Note:
16.2
16.3
16.4
Known limitations
PA2 limitation with OCMP1 enabled
Description
This limitation affects only Rev B Flash devices (with Internal Sales Type 72F63Bxxxxx$x7
it has been corrected in Rev W Flash devices (with Internal Sales Type 72F63Bxxxxx$x9
Refer to
When output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in
the TCR2 register, pin PA2 is also affected.
In particular, PA2 is switched to its alternate function mode, SCL. As a consequence, the
PA2 pin is forced to be floating (steady level of I
(PADDR+PADR) has set it as output low. However, it can be still used as an input or can be
controlled by the I
Unexpected RESET fetch
Description
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
USB behavior with LVD disabled
Description
If the LVD is disabled on 4K and 8K ROM devices (ST7263BK1M1, ST72BK2M1,
ST7263BKB1, ST7263BK2B1 only), the USB is disabled by hardware. The LVD is
consequently forced by ST to ‘0’ (LVD enabled). Refer to the ST7263Bx option list for details.
I
Description
In multimaster configurations, if the ST7 I
master after the START bit is set in the I2CCR register and before the START condition is
generated by the ST7 I
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a re-start and Slave address to re-initiate communication
2
C multimaster
Figure 85 on page 183
2
C cell when enabled (where I
2
C, it may ignore the START condition from the other I
Doc ID 7516 Rev 8
2
C receives a START condition from another I
2
2
C clock) even if port configuration
C is available).
Known limitations
2
C master. In
181/186
2
C
)
.
)
;