ST7263BK1 STMicroelectronics, ST7263BK1 Datasheet - Page 90

• Manufacturer Part Number: ST7263BK1
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BK1

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

On-chip peripherals
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Register description
Status register (SCISR)
Reset value: 1100 0000 (C0h)
TDRE
7
7 TDRE Transmit data register empty.
6 TC Transmission complete.
5 RDRF Received data ready flag.
4 IDLE Idle line detect.
This bit is set by hardware when the content of the TDR register has been
transferred into the shift register. An interrupt is generated if the TIE bit=1 in the
SCICR2 register. It is cleared by a software sequence (an access to the SCISR
register followed by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data will not be transferred to the shift register unless the TDRE bit is
This bit is set by hardware when transmission of a frame containing Data is
complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by
a software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE=1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if
the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a
TC
cleared.
new idle line occurs).
RDRF
Doc ID 7516 Rev 8
IDLE
Read only
OR
NF
FE
ST7263Bxx
PE
0