DS80CH11 Maxim, DS80CH11 Datasheet - Page 34

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

6.2 REGISTER DESCRIPTION
The microcontroller interface to either 2–Wire serial port
consists of six Special Function Registers (SFR’s), per
6.2.1
2WFS1; SFR ADDR.=09CH, 2WFS2; SFR ADDR.=0D3H
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The 2–Wire Frequency Select Registers are 8–bit read/
write registers which are used by the microcontroller to
set the 2–Wire clock data rate. The value programmed
into these registers sets the reload value for an 8–bit
auto–reload timer, which is clocked by the CPU
machine clock (t
The CPU machine clock period is the oscillator clock
period (t
mined by the programming of the system clock divider
6.2.2
2WDAT1; SFR ADDR.=09BH, 2WDAT2; SFR ADDR.=0D2H
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
The Data I/O Registers consist of transmit buffers and
the receive buffers. Both registers are located at SFR
address 9BH for Port 1 and D2H for Port 2. A write to
these locations results in a write to the transmit buffer
registers, while a read results in a read from the receive
buffer registers.
6.2.3
2WSADR1; SFR ADDR.=09AH, 2WSADR2; SFR ADDR.=0D1H
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
SLA6–0 – Slave Address bits
SLA6–0 are used to establish the 7–bit address recog-
nized by the 2–Wire port when it is operating in slave
DS80CH11
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BIT 7
BIT 7
BIT 7
SLA6
CLK
2WFSx – 2–Wire Frequency Select Registers
2WDATx – 2–Wire Data I/O Registers
2WSADRx – 2–Wire Slave Address Registers
) multiplied times 4, 64, or 1024 as deter-
MCLK
BIT 6
BIT 6
BIT 6
SLA5
) through a divide–by–8 prescaler.
BIT 5
BIT 5
BIT 5
SLA4
BIT 4
BIT 4
BIT 4
SLA3
Port, which are documented below. None of these reg-
isters are bit addressable.
bits (CD1, CD0) in the PMR register. The 2–wire clock
frequency can therefore be calculated using the follow-
ing formula:
f
where
During transmit, a write to these locations results in
8–bits of data being transmitted on the 2–Wire bus when
either master or slave transmit mode is established.
When master or slave receive mode is in effect, 8–bits
are shifted in via the shift register and immediately
transferred to the receive buffer. All data is shifted MSB
first.
mode. The 7–bit slave address is MSB justified when it
is read or written by the firmware. When read, bit 0 is
always returned as a 0.
2Wx
BIT 3
BIT 3
BIT 3
SLA2
= f
MCLK
Reload=(2WFSx register value) for 2–255,
and
Reload=(256) for 2WFSx value=0
Reload=(1) is invalid
/((8 * Reload) +2); t
BIT 2
BIT 2
BIT 2
SLA1
BIT 1
BIT 1
BIT 1
SLA0
2WCL
= 1 / f
2Wx
BIT 0
BIT 0
BIT 0
–