DS80CH11 Maxim, DS80CH11 Datasheet - Page 52

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

8.0 ACTIVITY MONITOR/LED CONTROL
8.1 OVERVIEW
During periods of inactivity, varying levels of standby
and suspend modes of operation can be initiated by the
SEM. Inactivity can be detected by the SEM and then
action can be taken to reduce the power consumption of
the system and thereby conserve operating power.
Activity monitoring is performed by the special logic pro-
vided as an alternate function on all lines of Port 7. This
alternate function allows any combination of the Port 7
pins to be configured as activity monitor inputs. In this
mode, these pins are intended for connection to the chip
select signals of external peripheral subsystems, such
as the hard disk, floppy, etc. These pins can be option-
ally qualified by the IOR and IOW input control signals.
When inactivity is detected, peripheral devices such as
the LCD display, hard disk, floppy disk, and modem are
turned off as required by the microcontroller firmware.
This is accomplished via parallel I/O pins as assigned by
the user. When CPU accesses to memory or I/O loca-
tions which are connected to the activity monitor inputs
are detected, accessed peripheral devices can be
turned back on by the firmware. As an option, the host
CPU can be notified of the power on sequence by writ-
ing a word to a power management host interface port,
which activates either SMI1 or SMI2.
8.2 ACTIVITY MONITOR INPUT
OPERATION
The activity monitor enable bits in the Activity Monitor
Enable (AME–092H) register select the associated pins
from Port 7 as activity monitor inputs. In order to func-
tion properly, each enabled pin must have a 1 pro-
grammed into its Port 7 output latch bit. The current
state of the Port 7 pins can always be read through the
Port 7 input buffer regardless of the programming of the
activity monitor enable bits. Figure 8–1 shows the logic
associated with each Activity Monitor Input.
The active state for each pin is programmed via the
Activity Monitor Polarity register (AMP–094H). A “0”
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programmed into a bit in the AMP register selects a low
state signal as active for the pin (default case) while a “1”
selects a high state signal.
When an active state is detected on an enabled activity
monitor pin, the associated bit in the Activity Monitor
Flag (AMF–095H) will be set.
In order to avoid false triggering of the activity monitor
inputs due to glitches from an external address decoder,
the inputs can be optionally qualified by the IOR and
IOW lines via the Activity Monitor Qualify register
(AMQ–093H). When a bit is set to 1 in the AMQ register,
the associated pin will not be active unless it is accom-
panied by a valid IOR or IOW signal. When AMQ bits
are 0, the associated pins qualify function is disabled
(default case).
Interrupts initiated from the enabled activity monitor pins
are enabled by the EAM bit (IE.6), and their priority can
be adjusted via PAM (IP.6). When activity monitor inter-
rupts are enabled and an active state occurs, an inter-
rupt will be generated, and the SEM firmware should
read the AMF register to determine the source of the
interrupt. The interrupt flag can be cleared by writing a
“0” to the flag bit; writing a 1 will have no effect.
When all peripheral devices in the system are fully pow-
ered, host accesses to them may occur very often. So
often in fact, that if these accesses were to initiate inter-
rupts during this time the SEM may be bogged down in
unnecessary interrupt service routines servicing the
interrupts. Typically, it is necessary only to ascertain
whether each monitored device has been accessed by
the host over the past, say, 16–second period. In order
to eliminate any unnecessary interrupt processing bur-
den, it may be desirable to disable the interrupts from
the activity monitor inputs (e.g., by clearing EAM) and
reading the register once during each such period. This
period can be easily set up via the Power Down Periodic
Interrupt described below.