DS80CH11 Maxim, DS80CH11 Datasheet - Page 36

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

port will generate an interrupt for every action on the bus
even when it is not operating as a master or being
addressed as a slave. As a result, when a transfer takes
place between an external master and slave, the port
will be notified of a transmitted START condition, will
receive the subsequent address and data bytes on the
6.2.5
2WSTAT11; SFR ADDR.=09EH, 2WSTAT12; SFR ADDR.=0DAH
Read/Write Access: Unrestricted.
Initialization: 00H on any type of reset
BERx – Bus ERror
BERx is a status flag which will be set to 1 in the event
that a stop condition is received with greater or less than
8 bits shifted. BERx is cleared when the 2WSTAT1x
register is read.
ARLx – ARbitration Loss
This bit is set to a 1 when the 2–Wire hardware loses
arbitration to another master on the bus. ARLx is
cleared when the 2WSTAT1x register is read. If arbitra-
tion is lost, the bus will enter the not–addressed slave
state and will receive data beginning with the byte where
arbitration was lost.
RSTOx – Received STOP
RSTOx is set when a valid stop condition is received
when operating as a slave. RSTOx is cleared when the
2WSTAT1x register is read.
TXIx – Transmit Interrupt Flags
During transmit, TXIx is set when a byte has been com-
pletely shifted out and the acknowledge bit received
from the slave. The TXIx flag must be cleared by firm-
6.2.6
2WSTAT21; SFR ADDR.=09FH, 2WSTAT22; SFR ADDR.=0DBH
Read/Write Access: Read Only.
Initialization: 00H on any type of reset
DS80CH11
011200 36/88
BERx
BIT 7
BIT 7
BBx
2WSTAT1x – 2–Wire Status Register 1
2WSTAT2x – 2–Wire Status Register 2
ADMx
BIT 6
ARLx
BIT 6
RSTOx
BIT 5
BIT 5
X/Rx
ACKSx
BIT 4
BIT 4
TXIx
bus, and will finally be notified of a transmitted STOP
condition.
ANAKx – Assert Negative AcKnowledge
If ANAKx is set to 1, a negative acknowledge bit will be
returned on the next serial word received. If it is 0, a pos-
itive acknowledge bit will be returned.
ware before any data written to the transmit buffer can
be transmitted, or after setting STAx or STOx bits. If
TXIx is not cleared the 2–Wire bus will be held low until it
is cleared.
RXIx – Receive Interrupt Flags
During receive, RXIx is set when the receive buffer reg-
ister is loaded with a byte of data which has just been
shifted in. The RXIx flag must be cleared by firmware
before the next byte of data can be shifted in.
TSTAx – Transmitted Start
TSTAx will be set to a 1 when a START condition has
been successfully transmitted on the 2–Wire bus. The
TSTAx must be cleared by firmware before the trans-
mission can begin if not the 2–Wire bus will be held low
until it is cleared.
RSTAx – Received Start
RSTAx = 1 when a START condition has been detected
on the bus. RSTAx will be cleared to 0 when the
2WSTAT1x register is read. If BMMx = 0, RSTAx does
not affect the setting of 2WIFx. If BMMx = 1, then RSTAx
will set 2WIFx.
BIT 3
BIT 3
RXIx
–
TSTAx
BIT 2
BIT 2
–
RSTAx
BIT 1
BIT 1
–
BIT 0
BIT 0
–
–