DS80CH11 Maxim, DS80CH11 Datasheet - Page 61

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

PWM CHANNEL CLOCK GENERATOR (1 OF 4) Figure 11–2
11.4 PWM PULSE GENERATORS
Figure 11–3 illustrates the pulse generators for each of
the four PWM channels. Each pulse generator has an
8–bit free running timer which accepts a clock input from
the associated PWM clock generator. The timer value is
compared to zero and to a user selectable value. Each
time that the timer value reaches zero (once every 256
clocks), the zero comparator sets a flip–flop. When the
timer reaches the user–selected PWM match value, this
comparator clears the flip–flop. The user–selected
PWM value thereby determines the PWM duty cycle.
If the channel’s associated output enable bit is set
(PWnOE), the output of this flip–flop is driven on the
associated port 6 pin. Note that when the output enable
bit is set, a full complementary push–pull driver is
enabled on the corresponding pin, replacing the
weak–p pull–up. When the PWnOE bit is set, the
associated general purpose port bit function is logically
disconnected from the pin.
The zero rollover condition will cause an “interrupt” flag
to be set for the associated channel. However, there is
no interrupt vector in the SEM which is dedicated to any
PWM channel’s flag. As a result, the flag is useful only
for polling purposes.
PWI.n
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/1
/4
1/4
EN
DIVIDE–BY–N COUNTER
8–BIT AUTO–RELOAD
PWM n FREQUENCY
SELECT REGISTER
The PWM compare value can be read from or written to
the PWM n SFR with the PWnT/C bit for the pair of PWM
channel’s cleared to 0. The PWM channel timer value
can be accessed via the PWM n SFR register with the
PWnT/C bit set to 1. The PWM value will be transferred
from the SFR to the comparator after the next match
occurs. Thus a selection value can be changed once
per 256 clocks. This prevents software from creating
glitches on the PWM pin. The comparator match flag
indicates when a match occurs and consequently when
the new value has been updated. At this time, software
can change the duty cycle if desired for update on the
next cycle.
A PWM value of 00h will create a PWM output that is
always zero. This is deglitched to prevent a simulta-
neous set and reset. A PWM value of FFh will create a
waveform that is high for 255 of 256 clocks. A DC over-
ride bit is provided for each channel which forces a
constant “1” state on the PWM output.
All PWM functions described above are duplicated for
all four PWM channels. For each, there is a single value
SFR used to access the channel’s Timer value and a
PWM value registers, a timer/compare select bit, an out-
put enable bit, a DC override bit, and a rollover flag bit.
PWM n CLOCK
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DS80CH11