DS80CH11 Maxim, DS80CH11 Datasheet - Page 72

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

the system under the control of the VRST pin is pre-
pared for a power down condition should it occur while
STOP with the band–gap disabled is in effect.
The control of the band–gap reference is located in the
Extended Interrupt Flag register (EXIF; 91h). Setting
BGS (EXIF.0) to a 1 will keep the band–gap reference
enabled during STOP mode. The default or reset condi-
tion is with the bit at a logic 0. This results in the band–
gap being off during STOP mode. Note that this bit has
no control of the reference during full power, Slow Clock
Mode, or IDLE modes.
The second feature allows an additional power saving
option while also making STOP easier to use. This is the
ability to start instantly when exiting STOP mode. It is
the internal ring oscillator that provides this feature.
This ring can be a clock source when exiting STOP
mode in response to an interrupt. The benefit of the ring
oscillator is as follows.
Using STOP mode turns off the crystal oscillator and all
internal clocks to save power. This requires that the
oscillator be restarted when exiting STOP mode. Actual
start–up time is crystal dependent, but is normally at
least 4 mS. A common recommendation is 10 mS. In an
application that will wake–up, perform a short operation,
then return to sleep, the crystal start–up can be longer
than the real transaction. However, the ring oscillator
will start instantly. Running from the ring, the user can
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perform a simple operation and return to sleep in less
time than it takes to start the crystal. If a user selects the
ring to provide the start–up clock and the processor
remains running, hardware will automatically switch to
the crystal once a power–on reset interval (65536
clocks) has expired.
assure proper crystal start even though power is not
being cycled.
The ring oscillator runs at approximately 4 MHz but will
not be a precise value. Do not conduct real–time preci-
sion operations (including serial communication) during
this ring period. Figure 12–2 shows how the operation
would compare when using the ring, and when starting
up normally. The default state is to exit STOP mode
without using the ring oscillator.
The RGSL – Ring Select bit at EXIF.1 (EXIF; 91h) con-
trols this function. When RGSL = 1, the CPU will use the
ring oscillator to exit STOP mode quickly. As mentioned
above, the processor will automatically switch from the
ring to the crystal after a delay of 65,536 crystal clocks.
For a 3.57 MHz crystal, this is approximately 18 mS.
The processor sets a flag called RGMD– Ring Mode,
located at EXIF.2, that tells software that the ring is
being used. The bit will be a logic 1 when the ring is in
use. Attempt no serial communication or precision tim-
ing while this bit is set, since the operating frequency is
not precise.
Hardware uses this value to