71M6541F Maxim, 71M6541F Datasheet - Page 124

• Manufacturer Part Number: 71M6541F
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6541D/F/G and 71M6542F/G Data Sheet
124
Name
VSTAT[2:0]
WAKE_ARM
WAKE_TMR[7:0]
WD_RST
WF_DIO4
WF_DIO52
WF_DIO55
WF_TMR
WF_PB
WF_RX
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
SFR F9[2:0]
Location
2880[7:0]
28B2[5]
28B4[7]
28B1[2]
28B1[1]
28B1[0]
28B1[5]
28B1[3]
28B1[4]
28B0[7]
28B0[6]
28B0[5]
28B0[4]
28B0[3]
28B0[2]
Rst Wk Dir
–
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
–
–
–
0
–
–
–
–
–
–
–
R/W
R/W Timer duration is WAKE_TMR+1 seconds.
W
R
R
R
R
R
R
R
R
Description
This word describes the source of power and the status of the VDD.
Arms the WAKE timer and loads it with WAKE_TMR[7:0]. When SLEEP or
LCD_ONLY is asserted by the MPU, the WAKE timer becomes active.
Reset the WD timer. The WD is reset when a 1 is written to this bit. Writing a
one clears and restarts the watch dog timer.
DIO4 wake flag bit. If DIO4 is configured to wake the part, this bit is set
whenever the de-bounced version of DIO4 rises. It is held in reset if DI04 is
not configured for wakeup.
DIO52 wake flag bit. If DIO52 is configured to wake the part, this bit is set
whenever the de-bounced version of DIO52 rises. It is held in reset if DI052 is
not configured for wakeup.
DIO55 wake flag bit. If DIO55 is configured to wake the part, this bit is set
whenever the de-bounced version of DIO55 rises. It is held in reset if DI055 is
not configured for wakeup.
Indicates that the wake timer caused the part to wake up.
Indicates that the PB caused the part to wake.
Indicates that RX caused the part to wake.
Indicates that the Reset pin, Reset bit, ERST pin, Watchdog timer, the cold
start detector, or bad VBAT caused the part to reset.
VSTAT Description
000
001
010
011
101
System Power OK. V3P3A>3.0v. Analog modules are functional
and accurate. [V3AOK,V3OK] = 11
System Power Low. 2.8v<V3P3A<3.0v. Analog modules not
accurate. Switch over to battery power is imminent.
[V3AOK,V3OK] = 01
Battery power and VDD OK. VDD>2.25v. Full digital functionality.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 11
Battery power and VDD>2.0. Flash writes are inhibited. If the
TRIMVDD[5] fuse is blown, PLL_FAST (I/O RAM 0x2200[4]) is
cleared.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 01
Battery power and VDD<2.0. When VSTAT=101, processor is
nearly out of voltage. Processor failure is imminent.
[V3AOK,V3OK] = 00, [VDDOK,VDDgt2] = 00
Rev 2