71M6541F Maxim, 71M6541F Datasheet - Page 144
71M6541F
Manufacturer Part Number
71M6541F
Description
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6541D.pdf
(166 pages)
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71M6541D/F/G and 71M6542F/G Data Sheet
6.4.9 2.5 V Voltage Regulator – Battery Power
Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BRN).
6.4.10 Crystal Oscillator
Measurement conditions: Crystal disconnected, test load of 200 pF/100 kΩ between XOUT and GNDD.
6.4.11 Phase-Locked Loop (PLL)
144
Parameter
V2P5
V2P5 load regulation
Voltage Overhead 2V − VBAT-VDD
Parameter
Maximum Output Power to Crystal
XIN to XOUT Capacitance
(see note 1)
Capacitance change on XOUT
Notes:
Parameter
PLL Power up Settling Time
(see note 1)
PLL_FAST settling time
PLL SLP to MSN Settling Time
(see note 2)
PLL power up overshoot
(see note 1)
Notes:
1.
1.
Guaranteed by design; not production tested.
PLL_FAST rise (see note 1)
PLL_FAST fall (see note 1)
Guaranteed by design; not production tested.
Table 104: Low-Power Voltage Regulator Performance Specifications
Table 105: Crystal Oscillator Performance Specifications
Table 106: PLL Performance Specifications
Condition
Crystal connected, see note 1
RTC_ADJ = 7F to 0,
Bias voltage = unbiased
Vpp = 0.1 V
Condition
VBAT = 3.0 V - 3.8 V,
V3P3 = 0 V, I
VBAT = 3.3 V, V3P3 = 0 V,
I
I
V3P3 = 0 V.
LOAD
LOAD
Condition
PLL_FAST = 0, V3P3 = 0 V to 3.3 V
step, measured from first edge of
MCK
V3P3 = 0 V, VBAT = 3.8 V to 2.0 V
PLL_FAST = 0
PLL_FAST = 0
= 0 mA to 1 mA
= 0ma, VBAT = 2.0 V,
LOAD
= 0 mA
2.55
Min
Min
Min
2.65
Typ
Typ
15
Typ
Max
Max
2.75
200
40
1
3
Max
2.5
5
5
5
5
Unit
Unit
mV
mV
μW
pF
pF
MHz
Rev 2
Unit
V
ms
ms
ms
ms
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