71M6541F Maxim, 71M6541F Datasheet - Page 64
![no-image](/images/no-image-200.jpg)
71M6541F
Manufacturer Part Number
71M6541F
Description
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6541D.pdf
(166 pages)
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71M6541D/F/G and 71M6542F/G Data Sheet
64
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
SEGDIO
Pin #
Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G)
Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F/G)
Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F/G)
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
16
28
16
16
16
0
SEGDIO
32
32
32
32
7
0
Pin #
LCD_MAP[23:16] (I/O RAM 0x2409)
17
27
17
17
17
1
33
33
33
33
6
1
18
25
18
18
18
2
34
34
34
34
5
2
LCD_MAP[39:32]
(I/O RAM 0x2407)
19
24
19
19
19
3
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
35
35
35
35
LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0]
3
4
51
53
51
51
51
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
0
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
20
23
20
20
20
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
4
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
(I/O RAM 0x2443[5:0] to 0x2447[5:0])
(I/O RAM 0x2420[0] to 0x242F[0])
36
36
36
36
(I/O RAM 0x2420[1] to 0x242F[1])
(I/O RAM 0x2430[0] to 0x243D[0])
(I/O RAM 0x2430[1] to 0x243D[1])
3
4
52
52
52
52
52
(I/O RAM 0x2443[0] to 0x2447[0])
(I/O RAM 0x2443[1] to 0x2447[1])
1
21
22
21
21
21
5
37
37
37
37
(I/O RAM 0x2405[7:3])
2
5
53
51
53
53
53
22
21
22
22
22
2
6
LCD_MAP[55:51]
38
38
38
38
23
20
23
23
1
6
54
47
54
54
54
23
7
3
100
24
19
24
24
39
39
39
39
24
7
0
55
46
55
55
55
4
LCD_MAP[31:24] (I/O RAM 0x2408)
25
18
25
25
25
1
40
99
40
40
40
0
–
–
–
–
–
–
26
17
26
26
26
2
(I/O RAM 0x2406[5:0])
41
98
41
41
41
1
–
–
–
–
–
–
LCD_MAP[45:40]
27
16
27
27
27
3
42
97
42
42
42
2
–
–
–
–
–
–
28
11
28
28
28
4
43
96
43
43
43
3
29
10
29
29
29
5
44
95
44
44
44
4
30
30
30
30
9
6
Rev 2
45
94
45
45
45
5
31
31
31
31
8
7
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