71M6541F Maxim, 71M6541F Datasheet - Page 56
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71M6541F
Manufacturer Part Number
71M6541F
Description
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6541D.pdf
(166 pages)
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For the 71M654x in BRN Mode, (with TEMP_PWR=TEMP_BSEL):
Table 46
71M6541D/F/G and 71M6542F/G Data Sheet
2.5.5 71M654x Temperature Sensor
The 71M654x includes an on-chip temperature sensor for determining the temperature of its bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system for the compensation of current, voltage and energy
measurement and the RTC. See
RTC Temperature Compensation
Unlike earlier generation Teridian SoCs, the 71M654x does not use the ADC to read the temperature
sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor can be used to compensate for the frequency variation
of the crystal, even in SLP mode while the MPU is halted. See
on page 53.
In MSN and BRN modes, the temperature sensor is awakened on command from the MPU by setting the
TEMP_START (I/O RAM 0x28B4[6]) control bit. The MPU must wait for the TEMP_START bit to clear before
reading STEMP[10:0] and before setting the TEMP_START bit once again. In SLP and LCD modes, it is
awakened at a regular rate set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]).
The result of the temperature measurement can be read from the two I/O RAM locations STEMP[10:3]
(I/O RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must
be read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in
resulting 11-bit value is in 2’s complement form and ranges from -1024 to +1023 (decimal). The equations
below are used to calculate the sensed temperature from the 11-bit STEMP[10:0] reading.
The equations below are used to calculate the sensed temperature. The first equation applies when the
71M654x is in MSN mode and TEMP_PWR = 1. The second equation applies when the 71M654x is in
BRN mode, and in this case, the TEMP_PWR and TEMP_BSEL bits must both be set to the same value, so
that the battery that supplies the temperature sensor is also the battery that is measured and reported in
BSENSE. Thus, the second equation requires reading STEMP and BSENSE. In the second equation,
BSENSE (the sensed battery voltage) is used to obtain a more accurate temperature reading when the IC
is in BRN mode.
For the 71M654x in MSN Mode (with TEMP_PWR = 1):
56
TBYTE_BUSY
TEMP_PER[2:0]
Name
measurement may not finish. In this case, firmware may complete the measurement by selecting
V3P3D (TEMP_PWR = 1).
If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature
shows the I/O RAM registers used for temperature and battery measurement.
Temp
Table 46: I/O RAM Registers for Temperature and Battery Measurement
(
o
28A0[2:0]
Location
C
28A0[3]
)
=
. 0
325
4.7 Metrology Temperature Compensation
⋅
Rst
STEMP
0
0
on page 53.
Temp
Wk
0
–
(
+
°
C
. 0
R/W
Dir
)
R
00218
=
. 0
325
Indicates that hardware is still writing the 0x28A0
byte. Additional writes to this byte are locked out
while it is one. Write duration could be as long as 6 ms.
Sets the period between temperature measurements.
Automatic measurements can be enabled in any
mode (MSN, BRN, LCD, or SLP).
Description
TEMP_PER
⋅
⋅
STEMP
BSENSE
1-6
0
7
+
2.5.4.4 RTC Temperature Compensation
22
2
−
Time
Manual updates (see TEMP_START)
2 ^ (3+TEMP_PER) (seconds)
Continuous
. 0
609
⋅
on page 97. Also see
BSENSE
Table
+
64
46). The
4 .
2.5.4.4
Rev 2