71M6541F Maxim, 71M6541F Datasheet - Page 29
71M6541F
Manufacturer Part Number
71M6541F
Description
The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6541D.pdf
(166 pages)
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71M6541D/F/G and 71M6542F/G Data Sheet
IB channel is a 71M6x01 isolated sensor, the sample data does not pass through the 71M6541D/F/G
multiplexer, as seen in
Figure
3. In this case, the sample is taken during the second half of the multiplexer
cycle and the data is directly stored in the corresponding CE RAM location as indicated in
Figure
3. The
timing relationship between the remote current sensor channel and its corresponding voltage is precisely
defined so that delay compensation can be properly applied by the CE.
Referring to
Figure
15, the 71M6542F/G features an additional voltage input (VB) permitting the
implementation of a two-phase meter. As with VA, the VB voltage divider is directly connected to the
71M6542F/G and uses the ADC and multiplexer facilities in the 71M6542F/G. MUX_DIV[3:0] = 4
configures the multiplexer to provide an additional time slot to accommodate the additional VB voltage
sample. As with the 71M6541D/F/G, IA samples are obtained from a current sensor that is directly
connected to the 71M6542F/G, while IB samples may be obtained from a directly connected CT or a
remotely connected shunt using a 71M6x01 isolated device as seen in
Figure 2
and
Figure
3.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM register
SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0]). The integration time for each energy output is:
SUM_SAMPS / 2520.6, where 2520.6 is the sample rate in Hz
For example, SUM_SAMPS = 2100 establishes 2100 samples per accumulation cycle, which has a
duration of 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the
MPU that accumulated data are available.
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
Figure 13
shows the accumulation interval resulting from SUM_SAMPS = 2100, consisting of 2100
samples of 397 µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied
to a 50 Hz signal. There is no correlation between the line signal frequency and the choice of
SUM_SAMPS. Furthermore, sampling does not have to start when the line voltage crosses the zero line,
and the length of the accumulation interval need not be an integer multiple of the signal cycles.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 13: Accumulation Interval
Rev 2
29
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