71M6541F Maxim, 71M6541F Datasheet - Page 60

• Manufacturer Part Number: 71M6541F
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6541D/F/G and 71M6542F/G Data Sheet
60
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as
shown in
to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. See
6.4.6 V3P3D Switch
Sourcing current in or out of DIO pins other than those dedicated for wake functions, for
example with pull-up or pull-down resistors, must be avoided. Violating this rule leads to
increased quiescent current in sleep and LCD modes.
Note:
Resources are selectable only on SEGDIO2 through SEGDIO11 and the
PB pin. See
Value in DIO_Rn[2:0]
Figure 20,
Not recommended
HIGH-Z
Figure 20: Connecting an External Load to DIO Pins
HIGH
LOW
5
Table 48
BROWNOUT
MISSION
LCD/SLEEP
right), not source it from V3P3D (as shown in
on page 143.
(71M6541D/F/G) and
DIO
V3P3SYS
V3P3D
GNDD
VBAT
Resource Selected for SEGDIOn or PB Pin
Low priority I/O interrupt (INT1)
Recommended
Table 52
HIGH-Z
HIGH
LOW
BROWNOUT
MISSION
LCD/SLEEP
(71M6542F/G).
DIO
V3P3SYS
VBAT
V3P3D
GNDD
Figure
20, left). This is due
Rev 2