11274-001 AMI Semiconductor, Inc., 11274-001 Datasheet - Page 31

• Manufacturer Part Number: 11274-001
• Description: Logic and Timing, Programmable Line Lock Clock Generator IC, Tape and Reel
• Manufacturer: AMI Semiconductor, Inc.

11.2
If a CMOS interface is desired, a transmission line is typi-
cally terminated using a series termination. Series termi-
nation adds no dc loading to the driver, and requires less
power than other resistive termination methods. In addi-
tion, no extra impedance exists from the signal line to a
reference voltage, such as ground.
Figure 28: Series Termination (CMOS)
As shown in Figure 28, the sum of the driver’s output im-
pedance (z
must equal the line impedance (z
When the source impedance (z
line impedance, then by voltage division the incident
wave amplitude is one-half of the full signal amplitude.
However, the full signal amplitude may take up to twice
as long as the propagation delay of the line to develop,
reducing noise immunity during the half-amplitude period.
Note that the voltage at the receive end must add up to a
signal amplitude that meets the receiver switching
thresholds. The slew rate of the signal may be reduced
due to the additional RC delay of the load capacitance
and the line impedance. Also, note that the output driver
impedance will vary slightly with the output logic state
(high or low).
CMOS Output Mode
O
DRIVER
) and the series termination resistance (R
V
i
V
z
R
O
(
z
S
O
(
z
O
R
z
S
R
L
S
R
)
O
LINE
z
S
L
z
+R
). That is,
O
)
L
z
.
L
S
) is matched to the
RECEIVE
V
2
S
)
31
11.3
Connection of devices to a standard-mode implementa-
tion of the I
Selection of the pull-up resistors (R
series resistors (R
on the supply voltage, the bus capacitance, and the
number of connected devices with their associated input
currents.
Control of the clock and data lines is done through open
drain/collector current-sink outputs, and thus requires
external pull-up resistors on both lines.
A guideline is
where t
and C
controller and 8 to 10 other devices on the bus, including
this one, results in values in the 5k
a series resistor to provide protection against high volt-
age spikes on the bus will alter the values for R
Figure 29: Connections to the Serial Bus
11.3.1
More information on the I
document The I
Specifications), available from Philips Semiconductors at
http://www-us2.semiconductors.philips.com.
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Programmable Line Lock Clock Generator IC
Clock Out
TRANSMITTER
SDA
(optional)
SCL
bus
r
R
Serial Communications
is the maximum rise time (minus some margin)
is the total bus capacitance. Assuming an I
S
For More Information
2
Data In
C-bus is similar to that shown in Figure 29.
R
Data Out
P
2
C-bus And How To Use It (Including
(optional)
S
) on the SDA and SCL lines depends
R
R
S
P
2
2
Clock In
C-bus can be found in the
RECEIVER
t
C
r
R
FS6131-01
FS6131-01
FS6131-01
FS6131-01
P
bus
(optional)
,
R
to 7k
S
P
) and the optional
Data In
Data Out
range. Use of
(optional)
P
.
R
S
2
C